1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a transistor and a method of manufacturing the same.
2. Description of the Related Art
Transistors, which are elements determining the electrical characteristics of a semiconductor device, have gate electrodes formed on a semiconductor substrate and source and drain regions formed in the semiconductor substrate and aligned on both sides of the gate electrodes. In order to insulate the gate electrodes from the source and drain regions, the transistor adopts spacers which are formed of a dielectric material at the sidewalls of the gate electrodes. These dielectric spacers serve as an ion implantation mask classifying heavily doped source/drain regions and lightly doped source/drain regions in a transistor having a lightly doped drain (LDD) structure. The spacers are formed of silicon oxide or silicon nitride.
However, as the integration density of semiconductor devices increases and in particular, the length of gate electrodes becomes 0.18 μm or less, the size of contact holes for connecting bit lines to source/drain regions and connecting storage electrodes to source/drain regions decreases and a margin for forming the contact holes decreases. Thus, the spacers are formed at the sidewalls of the gate electrodes of a material having an excellent etching selectivity to an interlevel dielectric layer filled inbetween the gate electrodes, thereby proposing a technique of forming the contact holes by a self-aligned method (hereinafter, referred to as a method of forming self-aligned contact holes). In general, a silicon, oxide layer is used as an interlevel dielectric layer and a silicon nitride layer is used for dielectric spacers in the method of forming self-aligned contact holes.
A method of forming self-aligned contact holes according to the prior art will be described with reference to FIGS. 1A through 1C.
FIG. 1A is a plan view of a semiconductor device having a transistor where self-aligned contact holes are formed, and FIGS. 1B and 1C are cross-sectional views taken along lines I—I and II—II, respectively, of FIG. 1A.
Gate oxide layers (not shown), gate electrodes formed of polysilicon patterns 12 and tungsten or tungsten silicide patterns 14 and silicon nitride layer patterns 16 are sequentially formed on a semiconductor substrate 10. Spacers 18 are formed of silicon nitride at the sidewalls of the gate electrodes and the silicon nitride layer patterns 16. Etch stoppers 20 and 22 are formed of silicon nitride at the sidewalls of the spacers 18 or on the semiconductor substrate 10. Source and drain regions 30 are formed inbetween gate electrodes in the semiconductor substrate 10. A contact hole 26b for a plug that electrically connects bit lines (not shown) to the source/drain regions 30 and contact holes 26a and 26c for plugs that electrically connects storage electrodes to the source/drain regions 30 are self-aligned and formed by a method using spacers 18 formed of silicon nitride and having an excellent etching selectivity of an interlevel dielectric layer 24 filled inbetween gate electrodes. The etch stoppers 20 and 22 prevent the semiconductor substrate 10 from being damaged when removing the interlevel dielectric layer 24 between the gate electrodes. However, the etch stopper 22 remains on the semiconductor substrate 10 in FIG. 1C where the interlevel dielectric layer 24 is not removed.
The dielectric constant of silicon oxide is 4, and the dielectric constant of silicon nitride is 7. Since spacers formed at the sidewalls of gate electrodes contact source/drain regions, the resistance-capacitance (RC) of a transistor adopting spacers formed of silicon nitride is high, thereby decreasing the operational speed of semiconductor devices.
Currently, a method of forming self-aligned contact holes is applied only to a cell area but may be applied to a peripheral circuit area if the integration density is increased. Thus, a problem of decreasing the operation speed of a row decoder, a column decoder, and a sense amplifier formed in the peripheral circuit area may be expected.
As a result, an attempt to form spacers of SiC, which has a low dielectric constant, was made. However, in a case of using SiC spacers, a process of manufacturing transistors having SiC spacers can only be developed after fully grasping the operational characteristics of semiconductor devices including changes in operational characteristics of transistors due to SiC.